Actually I'm using spidev_test utility from kernel source. My question would be if it's possible to configure SPI device below 2.5 MHz clock.
I've found similar device datasheet:
http://www.tracermcc.ru/foto/bender/RT3 ... 8_0902.pdfSPICFG register, SPICLK bits, recifies SPI clock divide control, which minimum value is: rate / 128. So given the fact that system clock is 320 MHz, it isn't possible to achieve less than 2.5 MHz ?